This invention relates to a memory incorporating logic LSI, in particular to a memory incorporating logic LSI provided with a circuit for testing it and a method for testing the same LSI.
Heretofore the test of the memory portion in a memory incorporating logic LSI has been effected, as disclosed in JP-B-57-3107 (corresponding to U.S. Pat. No. 4,074,851), while utilizing scan-in to a flipflop by applying a part of an input pattern to a flipflop provided with scanning function and the rest to an input terminal. In JP-A-61-204744 (corresponding U.S. Pat. No. 4,710,930) by the same inventors, a method, by which the memory portion is provided with scanning function and scan-in and scan-out to and from the memory portion are utilized, has been discussed.
According to all the prior art techniques described above, since the test has been effected by utilizing a scanning function, there has been a problem that dynamic function testing, by which the test is effected with a speed similar to that at the real operation time cannot be affected. As a method to solve this problem, a method is conceivable, by which all of the input and output signal lines of the memory are connected with external terminals (input and output terminal portion). However, by this method another problem is produced that many external terminals are necessary for the LSI.
The object of this invention is to provide a memory incorporating logic LSI and a method for testing the same LSI, with which it is possible to effect a dynamic function test of the memory portion without increasing the number of external terminals of the LSI and further to easily effect the test of the logic circuit portion.